typedef struct __acl_mem_blk_acl_key_t {
   uint32 data                 :              164;
} ds_acl_mem_blk_acl_key_t;

typedef struct __acl_mem_blk_key_type0_view0_t {
   uint32 valid                :                1;
   uint32 sport_bitmap         :               26;
   uint32 tcp_flag             :                6;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 l4_vld               :                1;
   uint32 fragment_flag        :                2;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 dip                  :               32;
   uint32 sip                  :               32;
   uint32 ip_vld               :                1;
   uint32 ethtype              :               16;
   uint32 ctag_status          :                2;
   uint32 stag_status          :                2;
   uint32 ctag                 :               16;
   uint32 stag                 :               16;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 rsv                  :               31;
} ds_acl_mem_blk_key_type0_view0_t;

typedef struct __acl_mem_blk_key_type0_view1_t {
   uint32 valid                :                1;
   uint32 sport_bitmap         :               26;
   uint32 reserved0            :                9;
   uint32 l2_payload           :              112;
   uint32 ip_vld               :                1;
   uint32 ethtype              :               16;
   uint32 ctag_status          :                2;
   uint32 stag_status          :                2;
   uint32 ctag                 :               16;
   uint32 stag                 :               16;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 rsv                  :               31;
} ds_acl_mem_blk_key_type0_view1_t;

typedef struct __acl_mem_blk_key_type1_view0_t {
   uint32 valid                :                1;
   uint32 sport_bitmap         :               26;
   uint32 reserved0            :               13;
   uint32 ip_vld               :                1;
   uint32 dip                  :              128;
   uint32 sip                  :              128;
   uint32 rsv                  :               31;
} ds_acl_mem_blk_key_type1_view0_t;

typedef struct __acl_mem_blk_key_type2_view0_t {
   uint32 valid                :                1;
   uint32 sport_bitmap         :               26;
   uint32 reserved0            :                2;
   uint32 udf_valid            :                8;
   uint32 udf_type             :                4;
   uint32 udf                  :              256;
   uint32 rsv                  :               31;
} ds_acl_mem_blk_key_type2_view0_t;

typedef struct __acl_mem_blk_key160_mac_view0_t {
   uint32 valid                :                1;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 ethtype              :               16;
   uint32 stag_status          :                1;
   uint32 stag                 :               16;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 range_bitmap         :               12;
   uint32 reserved0            :                2;
} ds_acl_mem_blk_key160_mac_view0_t;

typedef struct __acl_mem_blk_key160_macudf_view0_t {
   uint32 valid                :                1;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 ethtype              :               16;
   uint32 mac_addr             :               48;
   uint32 is_da                :                1;
   uint32 l4_type              :                3;
   uint32 l3_type              :                3;
   uint32 l2_type              :                2;
   uint32 udf_index            :                3;
   uint32 udf_01_valid         :                2;
   uint32 udf1                 :               32;
   uint32 udf0                 :               32;
   uint32 reserved0            :                1;
} ds_acl_mem_blk_key160_macudf_view0_t;

typedef struct __acl_mem_blk_key160_ethudf_view0_t {
   uint32 valid                :                1;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_type              :                3;
   uint32 l3_type              :                3;
   uint32 l2_type              :                2;
   uint32 udf_index            :                3;
   uint32 udf_valid            :                4;
   uint32 udf3                 :               32;
   uint32 udf2                 :               32;
   uint32 udf1                 :               32;
   uint32 udf0                 :               32;
} ds_acl_mem_blk_key160_ethudf_view0_t;

typedef struct __acl_mem_blk_key320_macipudf_view0_t {
   uint32 valid                :                2;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 dip                  :               32;
   uint32 sip                  :               32;
   uint32 l3_type              :                3;
   uint32 stag_status          :                1;
   uint32 svid                 :               12;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 udf_index            :                3;
   uint32 udf_01_valid         :                2;
   uint32 udf1                 :               32;
   uint32 udf0                 :               32;
   uint32 reserved0            :                1;
} ds_acl_mem_blk_key320_macipudf_view0_t;

typedef struct __acl_mem_blk_key160_ip_view0_t {
   uint32 valid                :                1;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 dip                  :               32;
   uint32 sip                  :               32;
   uint32 l3_type              :                3;
   uint32 range_bitmap         :               12;
   uint32 reserved0            :                4;
} ds_acl_mem_blk_key160_ip_view0_t;

typedef struct __acl_mem_blk_Key320_ipudf_view0_t {
   uint32 valid                :                2;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 dip                  :               32;
   uint32 sip                  :               32;
   uint32 l3_type              :                3;
   uint32 ethtype              :               16;
   uint32 stag_status          :                1;
   uint32 svid                 :               12;
   uint32 range_bitmap         :               12;
   uint32 udf_index            :                3;
   uint32 udf_valid            :                4;
   uint32 udf3                 :               32;
   uint32 udf2                 :               32;
   uint32 udf1                 :               32;
   uint32 udf0                 :               32;
   uint32 reserved0            :                3;
} ds_acl_mem_blk_Key320_ipudf_view0_t;

typedef struct __acl_mem_blk_Key640_macipv6_view0_t {
   uint32 valid                :                2;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 l3_type              :                3;
   uint32 ipaddr2              :               64;
   uint32 ipaddr1              :               64;
   uint32 ctag_status          :                1;
   uint32 stag_status          :                1;
   uint32 stag                 :               16;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 reserved0            :                1;
} ds_acl_mem_blk_Key640_macipv6_view0_t;

typedef struct __acl_mem_blk_Key320_ipv6_view0_t {
   uint32 valid                :                2;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 l3_type              :                3;
   uint32 dip                  :              128;
   uint32 sip                  :              128;
   uint32 reserved0            :                3;
} ds_acl_mem_blk_Key320_ipv6_view0_t;

typedef struct __acl_mem_blk_Key640_macipv6udf_view0_t {
   uint32 valid                :                4;
   uint32 key_type             :                4;
   uint32 sport_bitmap         :               14;
   uint32 port_type            :                2;
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 tcp_flag             :                6;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 tos                  :                8;
   uint32 ip_protocol          :                8;
   uint32 l3_type              :                3;
   uint32 dip                  :              128;
   uint32 sip                  :              128;
   uint32 ethtype              :               16;
   uint32 ctag_status          :                1;
   uint32 stag_status          :                1;
   uint32 ctag                 :               16;
   uint32 stag                 :               16;
   uint32 sa                   :               48;
   uint32 da                   :               48;
   uint32 range_bitmap         :               12;
   uint32 udf_index            :                3;
   uint32 udf_valid            :                4;
   uint32 udf3                 :               32;
   uint32 udf2                 :               32;
   uint32 udf1                 :               32;
   uint32 udf0                 :               32;
   uint32 reserved0            :               20;
} ds_acl_mem_blk_Key640_macipv6udf_view0_t;

typedef struct __arl_mem_blk_arl_table_t {
   uint32 port_id              :                6;
   uint32 dmac_filter          :                1;
   uint32 smac_filter          :                1;
   uint32 arl_type             :                2;
   uint32 station_moved        :                1;
   uint32 pending_learn        :                1;
   uint32 state                :                4;
   uint32 mstp                 :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_mem_blk_arl_table_t;

typedef struct __arl_mem_blk_mc_table_t {
   uint32 port_id              :               10;
   uint32 dmac_filter          :                1;
   uint32 smac_filter          :                1;
   uint32 arl_type             :                2;
   uint32 station_moved        :                1;
   uint32 pending_learn        :                1;
   uint32 state                :                4;
   uint32 mstp                 :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_mem_blk_mc_table_t;

typedef struct __arl_mem_blk_l2mc_mapping_table_t {
   uint32 mirror_en            :                1;
   uint32 egmirror_port_sel    :                6;
   uint32 bypass_evt           :                1;
   uint32 bypass_stp           :                1;
   uint32 dst_bitmap           :               26;
   uint32 lag_bitmap           :                5;
} ds_arl_mem_blk_l2mc_mapping_table_t;

typedef struct __arl_mem_blk_fid_learn_stat_table_t {
   uint32 learning_counter     :               14;
} ds_arl_mem_blk_fid_learn_stat_table_t;

typedef struct __arl_mem_blk_fid_learn_limit_table_t {
   uint32 learning_limit       :               14;
} ds_arl_mem_blk_fid_learn_limit_table_t;

typedef struct __arl_reg_blk_arl_ctrl_reg_t {
   uint32 da_update_disable    :                1;
   uint32 move_int_thd         :                8;
   uint32 move_int_timer       :               16;
   uint32 learn_int_thd        :                8;
   uint32 learn_int_timer      :               16;
   uint32 move_fifo_clr        :                1;
   uint32 learn_fifo_clr       :                1;
   uint32 uc_vid_sel           :                1;
   uint32 mc_vid_sel           :                1;
   uint32 sa0_not_learn        :                1;
   uint32 sa0_or_mc_drop       :                1;
   uint32 hash_sel             :                1;
   uint32 aging_en             :                1;
   uint32 sm_dir_ctrl          :                4;
   uint32 private_arl_type     :                2;
   uint32 hash_seed            :               32;
} ds_arl_reg_blk_arl_ctrl_reg_t;

typedef struct __arl_reg_blk_mac_lkup_ctrl_t {
   uint32 ipmc_enable          :                1;
   uint32 smac_filter          :                1;
   uint32 dmac_filter          :                1;
   uint32 bucket_full_to_fifo  :                1;
   uint32 new_learn_pending    :                1;
   uint32 station_move_pending :                1;
   uint32 learn_limit_enable   :                1;
   uint32 learn_to_static      :                1;
   uint32 new_enable           :                1;
   uint32 hw_move_enable       :                1;
   uint32 move_learn_mode      :                1;
   uint32 new_learn_mode       :                1;
   uint32 move_to_fifo         :                1;
   uint32 move_to_drop         :                1;
   uint32 overlimit_to_fifo    :                1;
   uint32 overlimit_to_drop    :                1;
   uint32 newsa_to_fifo        :                1;
   uint32 newsa_to_drop        :                1;
} ds_arl_reg_blk_mac_lkup_ctrl_t;

typedef struct __arl_reg_blk_port_nni_cfg_t {
   uint32 nni                  :               32;
} ds_arl_reg_blk_port_nni_cfg_t;

typedef struct __arl_reg_blk_cpu_search_ctrl_t {
   uint32 search_mc            :                1;
   uint32 search_start         :                1;
   uint32 search_type          :                3;
   uint32 direct_addr          :               16;
} ds_arl_reg_blk_cpu_search_ctrl_t;

typedef struct __arl_reg_blk_cpu_update_entry_t {
   uint32 port_id              :               10;
   uint32 dmac_filter          :                1;
   uint32 smac_filter          :                1;
   uint32 arl_type             :                2;
   uint32 station_moved        :                1;
   uint32 pending_learn        :                1;
   uint32 state                :                4;
   uint32 mstp                 :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_reg_blk_cpu_update_entry_t;

typedef struct __arl_reg_blk_cpu_search_status_t {
   uint32 learned              :                1;
   uint32 hit_miss             :                1;
   uint32 search_done          :                1;
} ds_arl_reg_blk_cpu_search_status_t;

typedef struct __arl_reg_blk_cpu_search_addr_t {
   uint32 table_ptr            :               16;
} ds_arl_reg_blk_cpu_search_addr_t;

typedef struct __arl_reg_blk_cpu_rdback_entry_t {
   uint32 port_id              :               10;
   uint32 dmac_filter          :                1;
   uint32 smac_filter          :                1;
   uint32 arl_type             :                2;
   uint32 station_moved        :                1;
   uint32 pending_learn        :                1;
   uint32 state                :                4;
   uint32 mstp                 :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_reg_blk_cpu_rdback_entry_t;

typedef struct __arl_reg_blk_age_timer_ctrl_t {
   uint32 aging_en             :                1;
   uint32 aging_r_trip         :               20;
   uint32 aging_entry          :               10;
} ds_arl_reg_blk_age_timer_ctrl_t;

typedef struct __arl_reg_blk_port_fast_aging_cfg_t {
   uint32 static_entry         :                1;
   uint32 glb_fast_aging       :                1;
   uint32 reserved0            :                1;
   uint32 port_id              :                6;
   uint32 enable               :                1;
} ds_arl_reg_blk_port_fast_aging_cfg_t;

typedef struct __arl_reg_blk_fid_fast_aging_cfg_t {
   uint32 enable               :                1;
   uint32 port_bitmap          :               31;
   uint32 static_entry         :                1;
   uint32 fid                  :                7;
} ds_arl_reg_blk_fid_fast_aging_cfg_t;

typedef struct __arl_reg_blk_mstp_fast_aging_cfg_t {
   uint32 enable               :                1;
   uint32 port_bitmap          :               31;
   uint32 static_entry         :                1;
   uint32 mstp                 :                6;
} ds_arl_reg_blk_mstp_fast_aging_cfg_t;

typedef struct __arl_reg_blk_mac_fast_aging_cfg_t {
   uint32 enable               :                1;
   uint32 ipmc_flag            :                1;
   uint32 port_bitmap          :               31;
   uint32 static_entry         :                1;
   uint32 mac                  :               48;
} ds_arl_reg_blk_mac_fast_aging_cfg_t;

typedef struct __arl_reg_blk_fast_aging_status_t {
   uint32 done                 :                1;
} ds_arl_reg_blk_fast_aging_status_t;

typedef struct __arl_reg_blk_aging_index_reg_t {
   uint32 aged_index           :               15;
} ds_arl_reg_blk_aging_index_reg_t;

typedef struct __arl_reg_blk_sendto_fifo_state_t {
   uint32 move_fifo_deep       :                7;
   uint32 move_fifo_empty      :                1;
   uint32 learn_fifo_deep      :                7;
   uint32 learn_fifo_empty     :                1;
} ds_arl_reg_blk_sendto_fifo_state_t;

typedef struct __arl_reg_blk_learn_fifo_reg_t {
   uint32 is_bucket_full       :                1;
   uint32 is_sa_overlimit      :                1;
   uint32 learn_as_pend        :                1;
   uint32 arl_type             :                2;
   uint32 port_id              :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_reg_blk_learn_fifo_reg_t;

typedef struct __arl_reg_blk_move_fifo_reg_t {
   uint32 is_sa_overlimit      :                1;
   uint32 is_move_done         :                1;
   uint32 learn_as_move        :                1;
   uint32 arl_type             :                2;
   uint32 table_portid         :                6;
   uint32 source_portid        :                6;
   uint32 fid                  :                7;
   uint32 mac_addr             :               48;
} ds_arl_reg_blk_move_fifo_reg_t;

typedef struct __arl_reg_blk_cpu_access_req_t {
   uint32 req                  :                1;
   uint32 req_type             :                1;
   uint32 page                 :                6;
   uint32 addr                 :               24;
} ds_arl_reg_blk_cpu_access_req_t;

typedef struct __arl_reg_blk_cpu_access_wdata_t {
   uint32 data                 :               16;
} ds_arl_reg_blk_cpu_access_wdata_t;

typedef struct __arl_reg_blk_cpu_access_rdata_t {
   uint32 complete             :                1;
   uint32 data                 :               16;
} ds_arl_reg_blk_cpu_access_rdata_t;

typedef struct __arl_reg_blk_portx_learn_stat_t {
   uint32 learning_counter     :               14;
} ds_arl_reg_blk_portx_learn_stat_t;

typedef struct __arl_reg_blk_portx_learn_limit_t {
   uint32 learning_limit       :               14;
} ds_arl_reg_blk_portx_learn_limit_t;

typedef struct __arl_reg_blk_hash_ctrl_t {
   uint32 hash_sel             :                2;
   uint32 seed                 :               32;
} ds_arl_reg_blk_hash_ctrl_t;

typedef struct __arl_reg_blk_mc_hash_ctrl_t {
   uint32 hash_sel             :                2;
   uint32 seed                 :               32;
} ds_arl_reg_blk_mc_hash_ctrl_t;

typedef struct __arl_reg_blk_arl_debug_reg_t {
   uint32 cam_used_cnt         :               16;
   uint32 da_hit_cnt           :               16;
   uint32 sa_hit_cnt           :               16;
} ds_arl_reg_blk_arl_debug_reg_t;

typedef struct __dma_reg_blk_dma_ctrl_t {
   uint32 rs                   :                1;
} ds_dma_reg_blk_dma_ctrl_t;

typedef struct __dma_reg_blk_dma_status_t {
   uint32 comp_cnt             :                8;
   uint32 comp_err_cnt         :                4;
   uint32 bus_err_cnt          :                4;
   uint32 timeout_cnt          :                4;
   uint32 halted_cnt           :                4;
   uint32 reserve              :                1;
   uint32 empty                :                1;
   uint32 idle                 :                1;
   uint32 halted               :                1;
} ds_dma_reg_blk_dma_status_t;

typedef struct __dma_reg_blk_dma_descrptr_t {
   uint32 head_ptr             :               32;
} ds_dma_reg_blk_dma_descrptr_t;

typedef struct __dma_reg_blk_dma_glb_ctrl_t {
   uint32 comp_wait_timer      :               16;
   uint32 comp_mode            :                1;
   uint32 tran_byte_type       :                1;
   uint32 burst_size           :                3;
} ds_dma_reg_blk_dma_glb_ctrl_t;

typedef struct __dma_reg_blk_dma_int_t {
   uint32 irq_delay            :                8;
   uint32 irq_thd              :                8;
   uint32 err_irqen            :                1;
   uint32 dly_irqen            :                1;
   uint32 ioc_irqen            :                1;
} ds_dma_reg_blk_dma_int_t;

typedef struct __dma_reg_blk_dma_queue_t {
   uint32 dma_id               :               48;
} ds_dma_reg_blk_dma_queue_t;

typedef struct __dma_reg_blk_dma_dcb_status_t {
   uint32 compt                :                1;
   uint32 decerr               :                1;
   uint32 slverr               :                1;
   uint32 comperr              :                1;
   uint32 eof                  :                1;
   uint32 sof                  :                1;
   uint32 chain                :                1;
   uint32 reserve              :                9;
   uint32 length               :               16;
   uint32 buf_ptr              :               32;
   uint32 nxt_descr_ptr        :               32;
} ds_dma_reg_blk_dma_dcb_status_t;

typedef struct __dma_reg_blk_dma_descriptor_t {
   uint32 compt                :                1;
   uint32 decerr               :                1;
   uint32 slverr               :                1;
   uint32 comperr              :                1;
   uint32 eof                  :                1;
   uint32 sof                  :                1;
   uint32 chain                :                1;
   uint32 reserve              :                9;
   uint32 length               :               16;
   uint32 buf_ptr              :               32;
   uint32 nxt_descr_ptr        :               32;
} ds_dma_reg_blk_dma_descriptor_t;

typedef struct __global_reg_blk_version_t {
   uint32 version              :               32;
} ds_global_reg_blk_version_t;

typedef struct __global_reg_blk_global_int_en_t {
   uint32 gbl_int              :                1;
} ds_global_reg_blk_global_int_en_t;

typedef struct __global_reg_blk_global_int_mask_set_t {
   uint32 dma_err_int          :                4;
   uint32 dma_comp_int         :                4;
   uint32 fifo_err_int         :                1;
   uint32 half_duplex_int      :                1;
   uint32 ecc_err_int          :                1;
   uint32 move_fifo_int        :                1;
   uint32 learn_fifo_int       :                1;
   uint32 gbl_int              :                1;
} ds_global_reg_blk_global_int_mask_set_t;

typedef struct __global_reg_blk_global_int_mask_reset_t {
   uint32 dma_err_int          :                4;
   uint32 dma_comp_int         :                4;
   uint32 fifo_err_int         :                1;
   uint32 half_duplex_int      :                1;
   uint32 ecc_err_int          :                1;
   uint32 move_fifo_int        :                1;
   uint32 learn_fifo_int       :                1;
   uint32 gbl_int              :                1;
} ds_global_reg_blk_global_int_mask_reset_t;

typedef struct __global_reg_blk_global_int_status_set_t {
   uint32 dma_err_int          :                4;
   uint32 dma_comp_int         :                4;
   uint32 fifo_err_int         :                1;
   uint32 half_duplex_int      :                1;
   uint32 ecc_err_int          :                1;
   uint32 move_fifo_int        :                1;
   uint32 learn_fifo_int       :                1;
   uint32 gbl_int              :                1;
} ds_global_reg_blk_global_int_status_set_t;

typedef struct __global_reg_blk_global_int_status_reset_t {
   uint32 dma_err_int          :                4;
   uint32 dma_comp_int         :                4;
   uint32 fifo_err_int         :                1;
   uint32 half_duplex_int      :                1;
   uint32 ecc_err_int          :                1;
   uint32 move_fifo_int        :                1;
   uint32 learn_fifo_int       :                1;
   uint32 gbl_int              :                1;
} ds_global_reg_blk_global_int_status_reset_t;

typedef struct __global_reg_blk_int_pluse_width_t {
   uint32 cnt                  :               32;
} ds_global_reg_blk_int_pluse_width_t;

typedef struct __global_reg_blk_int_port_mode_t {
   uint32 mode                 :                1;
} ds_global_reg_blk_int_port_mode_t;

typedef struct __intf_reg_blk_rgmii_clk_phase_ctl_t {
   uint32 rx_adjust            :                4;
   uint32 tx_mode              :                1;
   uint32 tx_adjust            :                4;
} ds_intf_reg_blk_rgmii_clk_phase_ctl_t;

typedef struct __intf_reg_blk_mac_rx_ctrl_t {
   uint32 swap_mac             :                1;
   uint32 tag_aware_en         :                1;
   uint32 min_frame_len        :                2;
   uint32 reserved0            :                1;
   uint32 flow_control_en      :                1;
   uint32 crc_strip_en         :                1;
   uint32 crc_check_en         :                1;
   uint32 pre_check_en         :                1;
   uint32 loopback_en          :                1;
   uint32 port_en              :                1;
} ds_intf_reg_blk_mac_rx_ctrl_t;

typedef struct __intf_reg_blk_mac_tx_ctrl_t {
   uint32 eee_en               :                1;
   uint32 eee_wakeup_time_sel  :                2;
   uint32 pause_trig           :                1;
   uint32 pause_on_off         :                1;
   uint32 flow_control_en      :                1;
   uint32 crc_invert_en        :                1;
   uint32 crc_insert_en        :                1;
   uint32 pre_sel              :                1;
   uint32 ipg_sel              :                3;
   uint32 speed_sel            :                2;
   uint32 intf_type            :                3;
   uint32 duplex_mode          :                1;
   uint32 loopback_en          :                1;
   uint32 port_en              :                1;
} ds_intf_reg_blk_mac_tx_ctrl_t;

typedef struct __intf_reg_blk_pause_time_ctrl_t {
   uint32 value                :               16;
} ds_intf_reg_blk_pause_time_ctrl_t;

typedef struct __intf_reg_blk_pause_interval_ctrl_t {
   uint32 value                :                4;
} ds_intf_reg_blk_pause_interval_ctrl_t;

typedef struct __intf_reg_blk_max_frame_len_t {
   uint32 len                  :               14;
} ds_intf_reg_blk_max_frame_len_t;

typedef struct __intf_reg_blk_jumbo_frame_len_t {
   uint32 len                  :               14;
} ds_intf_reg_blk_jumbo_frame_len_t;

typedef struct __intf_reg_blk_pesudo_random_seed_t {
   uint32 seed                 :               16;
} ds_intf_reg_blk_pesudo_random_seed_t;

typedef struct __intf_reg_blk_jam_pattern_t {
   uint32 pattern              :               32;
} ds_intf_reg_blk_jam_pattern_t;

typedef struct __intf_reg_blk_mac_status_t {
   uint32 late_col_err         :               26;
   uint32 reserve              :                6;
   uint32 exc_col_err          :               26;
} ds_intf_reg_blk_mac_status_t;

typedef struct __intf_reg_blk_cpu_mac_ctrl_t {
   uint32 no_ptag_drop         :                2;
   uint32 cpu_en               :                2;
   uint32 mode                 :                1;
} ds_intf_reg_blk_cpu_mac_ctrl_t;

typedef struct __intf_reg_blk_eee_sleep_time_t {
   uint32 timer                :               25;
} ds_intf_reg_blk_eee_sleep_time_t;

typedef struct __intf_reg_blk_eee_wakeup_time_t {
   uint32 timer                :               16;
} ds_intf_reg_blk_eee_wakeup_time_t;

typedef struct __intf_reg_blk_debug_state_t {
   uint32 state                :               32;
} ds_intf_reg_blk_debug_state_t;

typedef struct __intf_reg_blk_mac_cnt_ctrl_t {
   uint32 clr                  :                1;
} ds_intf_reg_blk_mac_cnt_ctrl_t;

typedef struct __intf_reg_blk_mac_cnt_t {
   uint32 cnt                  :               48;
   uint32 gmii_raise           :               16;
   uint32 ge_eop               :               16;
   uint32 ge_sop               :               16;
   uint32 xg_eop               :               16;
   uint32 xg_sop               :               16;
} ds_intf_reg_blk_mac_cnt_t;

typedef struct __mib_mem_blk_mib_rx_t {
   uint32 rxgoodjumbos         :               32;
   uint32 rxjumbopkt           :               32;
   uint32 rxpkts1024tomaxpktoctets :               32;
   uint32 rxpkts512to1023octets :               32;
   uint32 rxpkts256to511octets :               32;
   uint32 rxpkts128to255octets :               32;
   uint32 rxpkts65to127octets  :               32;
   uint32 rxpkts64octets       :               32;
   uint32 rxpkts60to63octets   :               32;
   uint32 rxoutofrangeerrors   :               32;
   uint32 inrangeerrors        :               32;
   uint32 rxpausepkts          :               32;
   uint32 rxfcserrors          :               32;
   uint32 rxalignmenterrors    :               32;
   uint32 rxjabbers            :               32;
   uint32 rxfragments          :               32;
   uint32 rxoversizepkts       :               32;
   uint32 rxundersizepkts      :               32;
   uint32 rxunicastpkts        :               32;
   uint32 rxmulticastpkts      :               32;
   uint32 rxbroadcastpkts      :               32;
   uint32 rxgoodoctets         :               32;
   uint32 rxoctets             :               64;
} ds_mib_mem_blk_mib_rx_t;

typedef struct __mib_mem_blk_mib_tx_t {
   uint32 txmorethanjumbopkt   :               32;
   uint32 txjumbopkt           :               32;
   uint32 txpkts1024tomaxpktoctets :               32;
   uint32 txpkts512to1023octets :               32;
   uint32 txpkts256to511octets :               32;
   uint32 txpkts128to255octets :               32;
   uint32 txpkts65to127octets  :               32;
   uint32 txpkts64octets       :               32;
   uint32 txpkts60to63octets   :               32;
   uint32 txpausepkts          :               32;
   uint32 txunicastpkts        :               32;
   uint32 txmulticastpkts      :               32;
   uint32 txbroadcastpkts      :               32;
   uint32 txoctets             :               64;
} ds_mib_mem_blk_mib_tx_t;

typedef struct __mib_reg_blk_mib_cfg_t {
   uint32 mib_cmd_chn          :                5;
   uint32 mib_cmd_dir          :                1;
   uint32 snap_mode            :                1;
   uint32 mib_cmd              :                1;
   uint32 mib_cmd_en           :                1;
} ds_mib_reg_blk_mib_cfg_t;

typedef struct __mmu_mem_blk_ing_mmu_port_cnt_t {
   uint32 pkt_cnt              :               10;
   uint32 cell_cnt             :               12;
} ds_mmu_mem_blk_ing_mmu_port_cnt_t;

typedef struct __mmu_mem_blk_ing_mmu_port_ctrl_t {
   uint32 cell_head            :                9;
   uint32 cell_offset          :                9;
   uint32 cell_share           :                9;
   uint32 cell_dynamic         :                1;
   uint32 cell_min             :                9;
   uint32 pkt_head             :                8;
   uint32 pkt_offset           :                8;
   uint32 pkt_share            :                8;
   uint32 pkt_dynamic          :                1;
   uint32 pkt_min              :                8;
} ds_mmu_mem_blk_ing_mmu_port_ctrl_t;

typedef struct __mmu_mem_blk_ingress_mib_table_t {
   uint32 cnt                  :               32;
} ds_mmu_mem_blk_ingress_mib_table_t;

typedef struct __mmu_mem_blk_queue_min_max_t {
   uint32 bucket_grain         :                3;
   uint32 meter_mode           :                1;
   uint32 max_refresh_cnt      :               19;
   uint32 max_threshold        :               12;
   uint32 min_refresh_cnt      :               19;
   uint32 min_threshold        :               12;
   uint32 max_meter_en         :                1;
   uint32 min_meter_en         :                1;
} ds_mmu_mem_blk_queue_min_max_t;

typedef struct __mmu_mem_blk_queue_weight_t {
   uint32 weight               :                7;
} ds_mmu_mem_blk_queue_weight_t;

typedef struct __mmu_reg_blk_cpu_access_req_t {
   uint32 req                  :                1;
   uint32 req_type             :                1;
   uint32 page                 :                6;
   uint32 addr                 :               24;
} ds_mmu_reg_blk_cpu_access_req_t;

typedef struct __mmu_reg_blk_cpu_access_wdata_t {
   uint32 data                 :              256;
} ds_mmu_reg_blk_cpu_access_wdata_t;

typedef struct __mmu_reg_blk_cpu_access_rdata_t {
   uint32 complete             :                1;
   uint32 data                 :              256;
} ds_mmu_reg_blk_cpu_access_rdata_t;

typedef struct __mmu_reg_blk_ing_mmu_port_en_t {
   uint32 clr_all_debug        :                1;
   uint32 enable               :               26;
} ds_mmu_reg_blk_ing_mmu_port_en_t;

typedef struct __mmu_reg_blk_ing_mmu_xoff_en_t {
   uint32 enable               :               26;
} ds_mmu_reg_blk_ing_mmu_xoff_en_t;

typedef struct __mmu_reg_blk_ing_mmu_glb_cnt_t {
   uint32 pkt_cnt              :               10;
   uint32 cell_cnt             :               12;
} ds_mmu_reg_blk_ing_mmu_glb_cnt_t;

typedef struct __mmu_reg_blk_ing_mmu_glb_cnt_max_t {
   uint32 pkt_cnt              :               10;
   uint32 cell_cnt             :               12;
} ds_mmu_reg_blk_ing_mmu_glb_cnt_max_t;

typedef struct __mmu_reg_blk_ing_mmu_glb_state_t {
   uint32 pkt_state            :                2;
   uint32 cell_state           :                2;
   uint32 total_cell_share     :               12;
   uint32 total_pkt_share      :               10;
} ds_mmu_reg_blk_ing_mmu_glb_state_t;

typedef struct __mmu_reg_blk_ing_mmu_glb_ctrl_t {
   uint32 thd_drop_en          :                1;
   uint32 pkt_drop             :                8;
   uint32 pkt_pause            :                8;
   uint32 pkt_offset           :                8;
   uint32 pkt_share            :                8;
   uint32 cell_drop            :                9;
   uint32 cell_pause           :                9;
   uint32 cell_offset          :                9;
   uint32 cell_share           :                9;
} ds_mmu_reg_blk_ing_mmu_glb_ctrl_t;

typedef struct __mmu_reg_blk_ing_mmu_port_state_t {
   uint32 pkt_state            :                2;
   uint32 cell_state           :                2;
} ds_mmu_reg_blk_ing_mmu_port_state_t;

typedef struct __mmu_reg_blk_mmu_cell_pool_debug_t {
   uint32 pool_deep            :               15;
   uint32 pool_full            :                1;
   uint32 pool_empty           :                1;
   uint32 pool_tail_err        :                8;
   uint32 pool_full_err        :                8;
   uint32 pool_empty_drop      :               16;
   uint32 recycle_fifo_full_err :                8;
   uint32 assign_fifo_deep     :                6;
} ds_mmu_reg_blk_mmu_cell_pool_debug_t;

typedef struct __mmu_reg_blk_mmu_pkt_pool_debug_t {
   uint32 pool_deep            :               14;
   uint32 pool_full            :                1;
   uint32 pool_empty           :                1;
   uint32 pool_tail_err        :                8;
   uint32 pool_full_err        :                8;
   uint32 pool_empty_drop      :               16;
   uint32 recycle_fifo_full_err :                8;
   uint32 assign_fifo_deep     :                6;
} ds_mmu_reg_blk_mmu_pkt_pool_debug_t;

typedef struct __mmu_reg_blk_mmu_ing_cnt_debug_t {
   uint32 debug_drop           :               16;
   uint32 rrfifo_full_err      :                8;
   uint32 cell_updn_err        :                8;
   uint32 pkt_updn_err         :                8;
   uint32 glb_cnt_err          :                8;
   uint32 inport_ptrfifo_wrerr :                8;
   uint32 inport_ptrfifo_notready_err :                8;
   uint32 ing_ptr_len_err      :                8;
   uint32 reserved0            :                6;
   uint32 enqueue_wr_err       :               26;
   uint32 enq_zero_drop        :               32;
   uint32 ipe_drop             :               32;
   uint32 ing_ptr_full_drop    :               32;
} ds_mmu_reg_blk_mmu_ing_cnt_debug_t;

typedef struct __mmu_reg_blk_mmu_port_debug_t {
   uint32 bp_dis               :                1;
} ds_mmu_reg_blk_mmu_port_debug_t;

typedef struct __mmu_reg_blk_mmu_schedule_debug_t {
   uint32 port_queue_empty     :                8;
   uint32 sch_info_struct      :               56;
   uint32 egport_shape_inprofile :               32;
   uint32 port_is_empty        :               32;
} ds_mmu_reg_blk_mmu_schedule_debug_t;

typedef struct __mmu_reg_blk_ingress_mmu_mib_t {
   uint32 mib_cmd_chn          :                5;
   uint32 mib_cmd_dir          :                1;
   uint32 mib_cmd              :                1;
   uint32 mib_cmd_en           :                1;
} ds_mmu_reg_blk_ingress_mmu_mib_t;

typedef struct __mmu_reg_blk_eg_monitor_ctrl_t {
   uint32 mon_q_mode           :                2;
   uint32 mon_mode             :                1;
   uint32 mon_pid              :                6;
   uint32 mon_qid              :                8;
} ds_mmu_reg_blk_eg_monitor_ctrl_t;

typedef struct __mmu_reg_blk_eg_mon_port_cnt_t {
   uint32 total_cnt            :               12;
   uint32 yellow_cnt           :               12;
   uint32 red_cnt              :               12;
   uint32 min_state            :                1;
   uint32 drop_state           :                2;
} ds_mmu_reg_blk_eg_mon_port_cnt_t;

typedef struct __mmu_reg_blk_eg_mon_queue_cnt_t {
   uint32 shareuc_cnt          :               12;
   uint32 total_cnt            :               12;
   uint32 yellow_cnt           :               12;
   uint32 red_cnt              :               12;
   uint32 min_state            :                1;
   uint32 drop_state           :                2;
} ds_mmu_reg_blk_eg_mon_queue_cnt_t;

typedef struct __mmu_reg_blk_eg_mmu_glb_ctrl_t {
   uint32 share_thd            :                9;
   uint32 offset_thd           :                9;
   uint32 limit_yellow_thd     :                9;
   uint32 offset_yellow_thd    :                9;
   uint32 limit_red_thd        :                9;
   uint32 offset_red_thd       :                9;
} ds_mmu_reg_blk_eg_mmu_glb_ctrl_t;

typedef struct __mmu_reg_blk_eg_mmu_glb_state_t {
   uint32 total_cnt            :               12;
   uint32 share_cnt            :               12;
   uint32 yellow_cnt           :               12;
   uint32 red_cnt              :               12;
   uint32 drop_state           :                2;
} ds_mmu_reg_blk_eg_mmu_glb_state_t;

typedef struct __mmu_reg_blk_p_cell_min_profile_t {
   uint32 min_thd              :                9;
} ds_mmu_reg_blk_p_cell_min_profile_t;

typedef struct __mmu_reg_blk_p_cell_share_profile_t {
   uint32 share_thd            :                9;
} ds_mmu_reg_blk_p_cell_share_profile_t;

typedef struct __mmu_reg_blk_p_cell_offset_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_p_cell_offset_profile_t;

typedef struct __mmu_reg_blk_p_cell_limit_yellow_profile_t {
   uint32 thd                  :                9;
} ds_mmu_reg_blk_p_cell_limit_yellow_profile_t;

typedef struct __mmu_reg_blk_p_cell_offset_yellow_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_p_cell_offset_yellow_profile_t;

typedef struct __mmu_reg_blk_p_cell_limit_red_profile_t {
   uint32 thd                  :                9;
} ds_mmu_reg_blk_p_cell_limit_red_profile_t;

typedef struct __mmu_reg_blk_p_cell_offset_red_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_p_cell_offset_red_profile_t;

typedef struct __mmu_reg_blk_eg_port_thd_ctrl_t {
   uint32 min_index            :                3;
   uint32 share_index          :                3;
   uint32 offset_index         :                3;
   uint32 yellow_limit_index   :                3;
   uint32 red_limit_index      :                3;
   uint32 yellow_reset_index   :                3;
   uint32 red_reset_index      :                3;
} ds_mmu_reg_blk_eg_port_thd_ctrl_t;

typedef struct __mmu_reg_blk_q_cell_min_profile_t {
   uint32 min_thd              :                9;
} ds_mmu_reg_blk_q_cell_min_profile_t;

typedef struct __mmu_reg_blk_q_cell_share_profile_t {
   uint32 share_thd            :                9;
   uint32 dynamic_en           :                1;
} ds_mmu_reg_blk_q_cell_share_profile_t;

typedef struct __mmu_reg_blk_q_cell_offset_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_q_cell_offset_profile_t;

typedef struct __mmu_reg_blk_q_cell_limit_yellow_profile_t {
   uint32 thd                  :                9;
} ds_mmu_reg_blk_q_cell_limit_yellow_profile_t;

typedef struct __mmu_reg_blk_q_cell_offset_yellow_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_q_cell_offset_yellow_profile_t;

typedef struct __mmu_reg_blk_q_cell_limit_red_profile_t {
   uint32 thd                  :                9;
} ds_mmu_reg_blk_q_cell_limit_red_profile_t;

typedef struct __mmu_reg_blk_q_cell_offset_red_profile_t {
   uint32 offset               :                9;
} ds_mmu_reg_blk_q_cell_offset_red_profile_t;

typedef struct __mmu_reg_blk_eg_queue_thd_ctrl_t {
   uint32 min_index            :                4;
   uint32 share_index          :                4;
   uint32 offset_index         :                4;
   uint32 yellow_limit_index   :                3;
   uint32 red_limit_index      :                3;
   uint32 yellow_reset_index   :                3;
   uint32 red_reset_index      :                3;
} ds_mmu_reg_blk_eg_queue_thd_ctrl_t;

typedef struct __mmu_reg_blk_port_shape_t {
   uint32 meter_mode           :                1;
   uint32 meter_grain          :                3;
   uint32 max_refresh_cnt      :               19;
   uint32 max_threshold        :               12;
   uint32 max_meter_en         :                1;
} ds_mmu_reg_blk_port_shape_t;

typedef struct __mmu_reg_blk_sch_port_mode_t {
   uint32 quanta               :                2;
   uint32 wrr_mode             :                1;
   uint32 sp_bitmap            :                8;
} ds_mmu_reg_blk_sch_port_mode_t;

typedef struct __mmu_reg_blk_sch_glb_mode_t {
   uint32 min_max_ifg_bytes    :                5;
   uint32 ifg_bytes            :                5;
   uint32 itu_mode             :                1;
} ds_mmu_reg_blk_sch_glb_mode_t;

typedef struct __pe_mem_blk_ingress_mstp_table_t {
   uint32 stp_st_port25        :                3;
   uint32 stp_st_port24        :                3;
   uint32 stp_st_port23        :                3;
   uint32 stp_st_port22        :                3;
   uint32 stp_st_port21        :                3;
   uint32 stp_st_port20        :                3;
   uint32 reserved0            :                2;
   uint32 stp_st_port19        :                3;
   uint32 stp_st_port18        :                3;
   uint32 stp_st_port17        :                3;
   uint32 stp_st_port16        :                3;
   uint32 stp_st_port15        :                3;
   uint32 stp_st_port14        :                3;
   uint32 stp_st_port13        :                3;
   uint32 stp_st_port12        :                3;
   uint32 stp_st_port11        :                3;
   uint32 stp_st_port10        :                3;
   uint32 reserved1            :                2;
   uint32 stp_st_port9         :                3;
   uint32 stp_st_port8         :                3;
   uint32 stp_st_port7         :                3;
   uint32 stp_st_port6         :                3;
   uint32 stp_st_port5         :                3;
   uint32 stp_st_port4         :                3;
   uint32 stp_st_port3         :                3;
   uint32 stp_st_port2         :                3;
   uint32 stp_st_port1         :                3;
   uint32 stp_st_port0         :                3;
} ds_pe_mem_blk_ingress_mstp_table_t;

typedef struct __pe_mem_blk_egress_mstp_table_t {
   uint32 stp_st_port25        :                1;
   uint32 stp_st_port24        :                1;
   uint32 stp_st_port23        :                1;
   uint32 stp_st_port22        :                1;
   uint32 stp_st_port21        :                1;
   uint32 stp_st_port20        :                1;
   uint32 stp_st_port19        :                1;
   uint32 stp_st_port18        :                1;
   uint32 stp_st_port17        :                1;
   uint32 stp_st_port16        :                1;
   uint32 stp_st_port15        :                1;
   uint32 stp_st_port14        :                1;
   uint32 stp_st_port13        :                1;
   uint32 stp_st_port12        :                1;
   uint32 stp_st_port11        :                1;
   uint32 stp_st_port10        :                1;
   uint32 stp_st_port9         :                1;
   uint32 stp_st_port8         :                1;
   uint32 stp_st_port7         :                1;
   uint32 stp_st_port6         :                1;
   uint32 stp_st_port5         :                1;
   uint32 stp_st_port4         :                1;
   uint32 stp_st_port3         :                1;
   uint32 stp_st_port2         :                1;
   uint32 stp_st_port1         :                1;
   uint32 stp_st_port0         :                1;
} ds_pe_mem_blk_egress_mstp_table_t;

typedef struct __pe_mem_blk_iresolution_drop_mib_t {
   uint32 frame_cnt            :               32;
} ds_pe_mem_blk_iresolution_drop_mib_t;

typedef struct __pe_mem_blk_eresolution_drop_mib_t {
   uint32 frame_cnt            :               32;
} ds_pe_mem_blk_eresolution_drop_mib_t;

typedef struct __pe_mem_blk_ingress_ptag_data_t {
   uint32 opcode               :                3;
   uint32 inservice_meter_id   :               11;
   uint32 inservice_meter_dir  :                1;
   uint32 inservice_meter_mode :                1;
   uint32 is_inservice         :                1;
   uint32 oam_y1564            :                1;
   uint32 oam_port_based       :                1;
   uint32 ts_insert            :                3;
   uint32 ts_1588cf            :                2;
   uint32 ts_addtail           :                2;
   uint32 ts_mode              :                2;
   uint32 tscnt_offset         :                8;
   uint32 cnt_insert           :                3;
   uint32 cnt_addtail          :                2;
   uint32 cnt_mode             :                2;
   uint32 cnt_index            :               10;
   uint32 not_modify           :                1;
   uint32 use_this_qpdp        :                1;
   uint32 qpdp                 :                6;
   uint32 fid                  :               12;
   uint32 bitmap_mode          :                1;
   uint32 reserved0            :                1;
   uint32 bypass_egmeter       :                1;
   uint32 reserved1            :                1;
   uint32 bypass_egloopback    :                1;
   uint32 bypass_egstp         :                1;
   uint32 bypass_egvlan        :                1;
   uint32 reserved2            :                2;
   uint32 bypass_egacl         :                1;
   uint32 bypass_isvid         :                1;
   uint32 bypass_eap           :                1;
   uint32 bypass_inmeter       :                1;
   uint32 bypass_inprotect     :                1;
   uint32 bypass_inloopback    :                1;
   uint32 bypass_instp         :                1;
   uint32 bypass_invlan        :                1;
   uint32 bypass_learning      :                1;
   uint32 bypass_inspmac       :                1;
   uint32 bypass_inacl         :                1;
   uint32 port_mode            :                2;
   uint32 port_bitmap_l        :               17;
} ds_pe_mem_blk_ingress_ptag_data_t;

typedef struct __pe_mem_blk_egress_ptag_data_t {
   uint32 reserved0            :                1;
   uint32 cnt_index            :               10;
   uint32 dport_bitmap         :               26;
   uint32 internal_svid        :               12;
   uint32 local_color          :                2;
   uint32 local_pri            :                4;
   uint32 qp                   :                3;
   uint32 not_learning         :                1;
   uint32 ivt_chk_fail_tocpu   :                1;
   uint32 ivt_unknown_tocpu    :                1;
   uint32 ip_have_option       :                1;
   uint32 egmir_tocpu          :                1;
   uint32 ingmir_tocpu         :                1;
   uint32 acl_tocpu            :                1;
   uint32 pmac_tocpu           :                1;
   uint32 smac_tocpu           :                1;
   uint32 ptp_tocpu            :                1;
   uint32 oam_tocpu            :                2;
   uint32 cpu_ptag_tocpu       :                1;
   uint32 oam_ptag_tocpu       :                1;
   uint32 arl_cpucopy          :                4;
   uint32 src_port             :                6;
   uint32 spmac_index_vld      :                1;
   uint32 acl_index_vld        :                1;
   uint32 acl_index            :                8;
   uint32 ts_mode              :                2;
   uint32 tail_ts              :                1;
   uint32 tail_cnt             :                1;
   uint32 itag_status          :                2;
   uint32 otag_action          :                2;
   uint32 itag_action          :                2;
   uint32 oam_1588_type        :                2;
   uint32 ip_type              :                2;
   uint32 layer_type           :                3;
   uint32 vlan_num             :                3;
} ds_pe_mem_blk_egress_ptag_data_t;

typedef struct __pe_mem_blk_smac_act_t {
   uint32 valid                :                1;
   uint32 qp2cpu               :                6;
   uint32 change_qp2cpu        :                1;
   uint32 da_change            :                1;
   uint32 not_modify           :                1;
   uint32 tag_mode             :                2;
   uint32 bypass_loopback      :                1;
   uint32 bypass_protect       :                1;
   uint32 bypass_learn_drop    :                1;
   uint32 bypass_stp           :                1;
   uint32 bypass_evc_drop      :                1;
   uint32 bypass_eap_drop      :                1;
   uint32 bypass_learning      :                1;
   uint32 bypass_vlan_check    :                1;
   uint32 mirror_en            :                1;
   uint32 drop                 :                1;
   uint32 copy_to_cpu          :                1;
   uint32 redirect_port_bitmap :               26;
   uint32 redirect_lag_bitmap  :                5;
   uint32 redirect_enable      :                1;
   uint32 bitmap_mode          :                1;
} ds_pe_mem_blk_smac_act_t;

typedef struct __pe_mem_blk_pmac_act_t {
   uint32 valid                :                1;
   uint32 qp2cpu               :                6;
   uint32 change_qp2cpu        :                1;
   uint32 da_change            :                1;
   uint32 not_modify           :                1;
   uint32 tag_mode             :                2;
   uint32 bypass_loopback      :                1;
   uint32 bypass_protect       :                1;
   uint32 bypass_learn_drop    :                1;
   uint32 bypass_stp           :                1;
   uint32 bypass_evc_drop      :                1;
   uint32 bypass_eap_drop      :                1;
   uint32 bypass_learning      :                1;
   uint32 bypass_vlan_check    :                1;
   uint32 mirror_en            :                1;
   uint32 drop                 :                1;
   uint32 copy_to_cpu          :                1;
   uint32 redirect_port_bitmap :               26;
   uint32 redirect_lag_bitmap  :                5;
   uint32 redirect_enable      :                1;
   uint32 bitmap_mode          :                1;
} ds_pe_mem_blk_pmac_act_t;

typedef struct __pe_mem_blk_ivm_x_index_t {
   uint32 ivm_index            :               12;
} ds_pe_mem_blk_ivm_x_index_t;

typedef struct __pe_mem_blk_ivm_table_t {
   uint32 valid                :                1;
   uint32 counter_index        :               10;
   uint32 counter_enable       :                1;
   uint32 mirror_en            :                1;
   uint32 drop                 :                1;
   uint32 bypass_vlan_check    :                1;
   uint32 bypass_stp           :                1;
   uint32 swap_tag             :                1;
   uint32 tag_action_profile_ptr :                5;
   uint32 isvid_mode           :                1;
   uint32 police_index         :                6;
   uint32 police_mode          :                1;
   uint32 trust_pri_mode       :                2;
   uint32 pri_index            :                4;
   uint32 remark_dscp_mode     :                2;
   uint32 remark_dscp          :                6;
   uint32 remark_scos_mode     :                2;
   uint32 remark_ccos_mode     :                2;
   uint32 remark_scos          :                4;
   uint32 remark_ccos          :                4;
   uint32 svid                 :               12;
   uint32 cvid                 :               12;
} ds_pe_mem_blk_ivm_table_t;

typedef struct __pe_mem_blk_ivm_action_profile_t {
   uint32 dt_tag_action        :                4;
   uint32 dt_op_stag_action    :                2;
   uint32 dt_ip_ctag_action    :                2;
   uint32 sot_tag_action       :                4;
   uint32 sop_tag_action       :                4;
   uint32 sit_tag_action       :                4;
   uint32 sip_tag_action       :                4;
   uint32 ut_tag_action        :                4;
} ds_pe_mem_blk_ivm_action_profile_t;

typedef struct __pe_mem_blk_ivt_table_t {
   uint32 valid                :                1;
   uint32 no_nni_nni_fwd       :                1;
   uint32 no_uni_uni_fwd       :                1;
   uint32 iepp_2nd_hash        :                3;
   uint32 ipep_2nd_hash        :                3;
   uint32 fid                  :                7;
   uint32 ingress_mstp_group_index :                5;
   uint32 vlan_profile_index   :                7;
   uint32 nni_master           :                1;
   uint32 protection_working_path :                1;
   uint32 protect_mode         :                3;
   uint32 drop_protect_pkt_en  :                1;
   uint32 vlan_member          :               26;
} ds_pe_mem_blk_ivt_table_t;

typedef struct __pe_mem_blk_ivt_profile_t {
   uint32 bcast_mask_sel       :                2;
   uint32 unknown_ucast_mask_sel :                2;
   uint32 known_mcast_mask_sel :                2;
   uint32 unknown_mcast_mask_sel :                2;
   uint32 block_mask_a         :               26;
   uint32 block_mask_b         :               26;
   uint32 stc_en               :                1;
   uint32 stc_base_index       :                7;
   uint32 dlf_stc_en           :                1;
   uint32 mlf_stc_en           :                1;
   uint32 l2mc_stc_en          :                1;
   uint32 bc_stc_en            :                1;
   uint32 fid_cfg_sm           :                1;
   uint32 fid_cfg_sa           :                1;
   uint32 mlf_drop             :                1;
   uint32 ulf_drop             :                1;
   uint32 bc_drop              :                1;
   uint32 stpid_index          :                2;
   uint32 drop                 :                1;
   uint32 pri_sel              :                1;
   uint32 qos_mode             :                1;
   uint32 arl_type             :                2;
} ds_pe_mem_blk_ivt_profile_t;

typedef struct __pe_mem_blk_vlan_xlate_t {
   uint32 data                 :               44;
} ds_pe_mem_blk_vlan_xlate_t;

typedef struct __pe_mem_blk_xlate_mac_vlan_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               13;
   uint32 sa                   :               48;
   uint32 svid                 :               12;
   uint32 key_type             :                4;
   uint32 valid                :                2;
} ds_pe_mem_blk_xlate_mac_vlan_key_t;

typedef struct __pe_mem_blk_xlate_mac_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               25;
   uint32 sa                   :               48;
   uint32 key_type             :                4;
   uint32 valid                :                2;
} ds_pe_mem_blk_xlate_mac_key_t;

typedef struct __pe_mem_blk_xlate_ipv4_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               35;
   uint32 sip                  :               32;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                2;
} ds_pe_mem_blk_xlate_ipv4_key_t;

typedef struct __pe_mem_blk_xlate_ipv6_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               31;
   uint32 sip                  :              128;
   uint32 key_type             :                4;
   uint32 valid                :                4;
} ds_pe_mem_blk_xlate_ipv6_key_t;

typedef struct __pe_mem_blk_xlate_svlan_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               12;
   uint32 svid                 :               12;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                1;
} ds_pe_mem_blk_xlate_svlan_key_t;

typedef struct __pe_mem_blk_xlate_double_vlan_key_t {
   uint32 ivm_index            :                9;
   uint32 svid                 :               12;
   uint32 cvid                 :               12;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                1;
} ds_pe_mem_blk_xlate_double_vlan_key_t;

typedef struct __pe_mem_blk_xlate_cvlan_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               12;
   uint32 cvid                 :               12;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                1;
} ds_pe_mem_blk_xlate_cvlan_key_t;

typedef struct __pe_mem_blk_xlate_otag_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :                8;
   uint32 otag                 :               16;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                1;
} ds_pe_mem_blk_xlate_otag_key_t;

typedef struct __pe_mem_blk_xlate_itag_key_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :                8;
   uint32 itag                 :               16;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                1;
} ds_pe_mem_blk_xlate_itag_key_t;

typedef struct __pe_mem_blk_vlan_hash_view9_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               41;
   uint32 sip                  :               32;
   uint32 key_type             :                4;
   uint32 valid                :                2;
} ds_pe_mem_blk_vlan_hash_view9_t;

typedef struct __pe_mem_blk_xlate_mac_key0_t {
   uint32 ivm_index            :                9;
   uint32 reserved0            :               25;
   uint32 sip                  :              128;
   uint32 sport                :                6;
   uint32 key_type             :                4;
   uint32 valid                :                4;
} ds_pe_mem_blk_xlate_mac_key0_t;

typedef struct __pe_mem_blk_evt_table_t {
   uint32 valid                :                1;
   uint32 epep_2nd_hash        :                3;
   uint32 eepp_2nd_hash        :                3;
   uint32 stpid_index          :                2;
   uint32 ctpid_index          :                1;
   uint32 vlan_untag_map       :               26;
   uint32 pri_sel              :                1;
   uint32 qos_mode             :                1;
   uint32 egress_mstp_index    :                5;
   uint32 vlan_member          :               26;
} ds_pe_mem_blk_evt_table_t;

typedef struct __pe_mem_blk_acl_base_action_t {
   uint32 cpu_flowid           :                3;
   uint32 bypass_loopback      :                1;
   uint32 not_modify           :                1;
   uint32 nni_master           :                1;
   uint32 protection_working_path :                1;
   uint32 drop_protect_pkt_en  :                1;
   uint32 protect_mode         :                3;
   uint32 bypass_protect       :                1;
   uint32 bypass_learning      :                1;
   uint32 bypass_spmac         :                1;
   uint32 bypass_evt_check     :                1;
   uint32 bypass_ivt_check     :                1;
   uint32 bypass_egress_stp_state :                1;
   uint32 bypass_ingress_stp_state :                1;
   uint32 bypass_evc_drop      :                1;
   uint32 bypass_eap_drop      :                1;
   uint32 mirror_en            :                2;
   uint32 egmirror_port_sel    :                6;
   uint32 copy_to_cpu          :                1;
   uint32 drop                 :                1;
   uint32 loopback_enable      :                1;
   uint32 loopback_index       :                5;
   uint32 redirect_enable      :                1;
   uint32 redirect_port_bitmap :               26;
   uint32 redirect_lag_bitmap  :                5;
   uint32 bitmap_mode          :                1;
   uint32 exp_egress_port_bitmap :               26;
} ds_pe_mem_blk_acl_base_action_t;

typedef struct __pe_mem_blk_acl_qos_action_t {
   uint32 counter_index        :               10;
   uint32 counter_enable       :                1;
   uint32 police_mode          :                1;
   uint32 police_index         :                6;
   uint32 police_position      :                1;
   uint32 police_exp_dport     :                5;
   uint32 qp2cpu               :                6;
   uint32 change_qp2cpu        :                1;
   uint32 remark_scos_mode     :                2;
   uint32 remark_dscp_mode     :                2;
   uint32 remark_scos          :                4;
   uint32 remark_dscp          :                6;
   uint32 trust_pri_mode       :                2;
   uint32 pri_index            :                4;
} ds_pe_mem_blk_acl_qos_action_t;

typedef struct __pe_reg_blk_cpu_access_req_t {
   uint32 req                  :                1;
   uint32 req_type             :                1;
   uint32 page                 :                6;
   uint32 addr                 :               24;
} ds_pe_reg_blk_cpu_access_req_t;

typedef struct __pe_reg_blk_cpu_access_wdata_t {
   uint32 data                 :              256;
} ds_pe_reg_blk_cpu_access_wdata_t;

typedef struct __pe_reg_blk_cpu_access_rdata_t {
   uint32 complete             :                1;
   uint32 data                 :              256;
} ds_pe_reg_blk_cpu_access_rdata_t;

typedef struct __pe_reg_blk_cpu_access_hash_req_t {
   uint32 search_start         :                1;
   uint32 search_type          :                3;
   uint32 key_type             :                4;
   uint32 direct_addr          :               16;
} ds_pe_reg_blk_cpu_access_hash_req_t;

typedef struct __pe_reg_blk_cpu_access_hash_status_t {
   uint32 key_type             :                4;
   uint32 learned              :                1;
   uint32 hit_miss             :                1;
   uint32 search_done          :                1;
} ds_pe_reg_blk_cpu_access_hash_status_t;

typedef struct __pe_reg_blk_cpu_access_hash_addr_t {
   uint32 table_ptr            :               16;
} ds_pe_reg_blk_cpu_access_hash_addr_t;

typedef struct __pe_reg_blk_cpu_access_hash_wdata_t {
   uint32 data                 :              256;
} ds_pe_reg_blk_cpu_access_hash_wdata_t;

typedef struct __pe_reg_blk_cpu_access_hash_rdata_t {
   uint32 data                 :              256;
} ds_pe_reg_blk_cpu_access_hash_rdata_t;

typedef struct __pe_reg_blk_global_ctrl_t {
   uint32 cnt_rc_en            :                1;
   uint32 ilp_droped_by_oam    :                1;
   uint32 egmirror_port_sel    :                6;
   uint32 mirror_dport         :                6;
   uint32 reserved0            :                5;
   uint32 protect_ixg4_subport :                3;
   uint32 protect_ixg3_subport :                3;
   uint32 udf_offset_l4        :                3;
   uint32 udf_offset_ipv6      :                3;
   uint32 udf_offset_ipv4      :                3;
   uint32 udf_offset_l2        :                3;
   uint32 nni_tx_protection_switch :                2;
   uint32 nni_rx_protection_switch :                2;
   uint32 vlan_chk_fail_tocpu  :                1;
   uint32 vlan_unknown_tocpu   :                1;
   uint32 receive_bpdu_tocpu   :                1;
   uint32 pkt_1588_qos_enable  :                1;
   uint32 pkt_1588_meter_enable :                1;
} ds_pe_reg_blk_global_ctrl_t;

typedef struct __pe_reg_blk_to_cpu_action_t {
   uint32 not_modify           :               32;
} ds_pe_reg_blk_to_cpu_action_t;

typedef struct __pe_reg_blk_tocpu_qp_t {
   uint32 use_reason2qp        :                1;
   uint32 qp                   :                6;
} ds_pe_reg_blk_tocpu_qp_t;

typedef struct __pe_reg_blk_ingress_port_t {
   uint32 trunk_id             :                3;
   uint32 trunk_vld            :                1;
   uint32 spmac_groupid        :                4;
   uint32 ivm_groupid          :                3;
   uint32 qos_proc_mode        :                1;
   uint32 counter_enable       :                1;
   uint32 counter_index        :               10;
   uint32 remark_dscp_mode     :                2;
   uint32 remark_dscp          :                6;
   uint32 remark_scos_mode     :                2;
   uint32 remark_scos          :                4;
   uint32 remark_ccos          :                4;
   uint32 pri_index            :                4;
   uint32 trust_pri_mode       :                2;
   uint32 police_index         :                6;
   uint32 police_mode          :                1;
   uint32 local_pri            :                4;
   uint32 local_color          :                2;
   uint32 use_cvid_as_ovid     :                1;
   uint32 trust_vid            :                1;
   uint32 bc_mask              :               26;
   uint32 mlf_mask             :               26;
   uint32 ulf_mask             :               26;
   uint32 egress_port_mask     :               26;
   uint32 eap_block            :                1;
   uint32 stp_state            :                3;
   uint32 ethoam_enable        :                1;
   uint32 ipv6_option_tocpu    :                1;
   uint32 ipv4_option_tocpu    :                1;
   uint32 ieee1588v2_enable    :                1;
   uint32 ingress_1p_map_ena   :                1;
   uint32 mirror_en            :                1;
   uint32 stpid_enable         :                4;
   uint32 ctpid_enable         :                2;
   uint32 afterctagtpid_enable :                2;
   uint32 vlan_tpid_verify_enable :                1;
   uint32 no_1p_pkt            :                1;
   uint32 no_tag_pkt           :                1;
   uint32 no_untag_pkt         :                1;
   uint32 bypass_stp           :                1;
   uint32 bypass_vlan_check    :                1;
   uint32 pvid                 :               12;
   uint32 ivm_x_en             :                1;
   uint32 ivm_mode             :                2;
} ds_pe_reg_blk_ingress_port_t;

typedef struct __pe_reg_blk_stagtpid_t {
   uint32 tpid3                :               16;
   uint32 tpid2                :               16;
   uint32 tpid1                :               16;
   uint32 tpid0                :               16;
} ds_pe_reg_blk_stagtpid_t;

typedef struct __pe_reg_blk_ctagtpid_t {
   uint32 tpid1                :               16;
   uint32 tpid0                :               16;
} ds_pe_reg_blk_ctagtpid_t;

typedef struct __pe_reg_blk_afterctagtpid_t {
   uint32 tpid1                :               16;
   uint32 tpid0                :               16;
} ds_pe_reg_blk_afterctagtpid_t;

typedef struct __pe_reg_blk_ptagtpid_t {
   uint32 tpid_cpu             :               16;
   uint32 tpid_oam             :               16;
} ds_pe_reg_blk_ptagtpid_t;

typedef struct __pe_reg_blk_lag_hash_control_t {
   uint32 key_sel              :               10;
} ds_pe_reg_blk_lag_hash_control_t;

typedef struct __pe_reg_blk_host_mac_t {
   uint32 mac                  :               48;
} ds_pe_reg_blk_host_mac_t;

typedef struct __pe_reg_blk_spmac_uc_mac_t {
   uint32 mac                  :               48;
} ds_pe_reg_blk_spmac_uc_mac_t;

typedef struct __pe_reg_blk_host_ipv6_t {
   uint32 ip                   :              128;
} ds_pe_reg_blk_host_ipv6_t;

typedef struct __pe_reg_blk_host_ipv4_t {
   uint32 ip                   :               32;
} ds_pe_reg_blk_host_ipv4_t;

typedef struct __pe_reg_blk_ttl_cfg_t {
   uint32 ttl                  :                8;
} ds_pe_reg_blk_ttl_cfg_t;

typedef struct __pe_reg_blk_egress_port_t {
   uint32 evm_groupid          :                3;
   uint32 evm_mode             :                2;
   uint32 port_down            :                1;
   uint32 stp_block            :                1;
   uint32 eap_block            :                1;
   uint32 mirror_en            :                1;
   uint32 block_bc_flooding    :                1;
   uint32 block_mlf_flooding   :                1;
   uint32 block_ulf_flooding   :                1;
   uint32 bypass_stp           :                1;
   uint32 bypass_vlan_check    :                1;
   uint32 pri_index            :                4;
   uint32 qos_proc_mode        :                1;
   uint32 remark_scos          :                4;
   uint32 remark_scos_mode     :                2;
   uint32 remark_ccos_mode     :                2;
   uint32 remark_ccos          :                4;
   uint32 remark_dscp_mode     :                2;
   uint32 remark_dscp          :                6;
   uint32 port_tpid_enable     :                1;
   uint32 stpid_index          :                2;
   uint32 ctpid_index          :                1;
} ds_pe_reg_blk_egress_port_t;

typedef struct __pe_reg_blk_checksum_debug_t {
   uint32 ipv6_icmp_chksum_recalc_en :                1;
   uint32 ipv6_udp_chksum_recalc_en :                1;
   uint32 ipv6_tcp_chksum_recalc_en :                1;
   uint32 ipv4_icmp_chksum_recalc_en :                1;
   uint32 ipv4_udp_chksum_recalc_en :                1;
   uint32 ipv4_tcp_chksum_recalc_en :                1;
   uint32 ipv4_chksum_recalc_en :                1;
   uint32 ipv6_icmp_chksum_ctrl :                2;
   uint32 ipv6_udp_chksum_ctrl :                2;
   uint32 ipv6_tcp_chksum_ctrl :                2;
   uint32 ipv4_icmp_chksum_ctrl :                2;
   uint32 ipv4_udp_chksum_ctrl :                2;
   uint32 ipv4_tcp_chksum_ctrl :                2;
   uint32 ipv4_chksum_ctrl     :                2;
} ds_pe_reg_blk_checksum_debug_t;

typedef struct __pe_reg_blk_ingress_debug_cnt_t {
   uint32 dset_port            :               16;
   uint32 pkt_eop              :               16;
   uint32 pkt_sop              :               16;
   uint32 resol_out            :               16;
   uint32 parser_out           :               16;
   uint32 ivm_in               :               16;
   uint32 parser_in_eop        :               16;
   uint32 parser_in_sop        :               16;
} ds_pe_reg_blk_ingress_debug_cnt_t;

typedef struct __pe_reg_blk_egress_debug_cnt_t {
   uint32 edit_out             :               16;
   uint32 pkt_eop              :               16;
   uint32 pkt_sop              :               16;
   uint32 parser_in            :               16;
} ds_pe_reg_blk_egress_debug_cnt_t;

typedef struct __pe_reg_blk_debug_cnt_clr_t {
   uint32 egress_clr           :                1;
   uint32 ingress_clr          :                1;
} ds_pe_reg_blk_debug_cnt_clr_t;

typedef struct __pe_reg_blk_debug_reg_t {
   uint32 debug                :               32;
} ds_pe_reg_blk_debug_reg_t;

typedef struct __pe_reg_blk_debug_ctrl_t {
   uint32 en                   :                1;
   uint32 index                :                8;
} ds_pe_reg_blk_debug_ctrl_t;

typedef struct __pe_reg_blk_security_filter_rule_t {
   uint32 icmpv6_fragment      :                1;
   uint32 icmpv6_longping      :                1;
   uint32 icmpv4_longping      :                1;
   uint32 ip_frag_err          :                1;
   uint32 icmpv4_fragment      :                1;
   uint32 tcp_fragerror        :                1;
   uint32 tiny_tcp             :                1;
   uint32 tcp_synerror         :                1;
   uint32 tcp_synfinscan       :                1;
   uint32 tcp_xmasscan         :                1;
   uint32 tcp_nullscan         :                1;
   uint32 udp_blat             :                1;
   uint32 tcp_blat             :                1;
   uint32 ip_land              :                1;
   uint32 mac_land             :                1;
} ds_pe_reg_blk_security_filter_rule_t;

typedef struct __pe_reg_blk_dos_size_t {
   uint32 max_icmpv6_size      :               11;
   uint32 max_icmpv4_size      :               11;
} ds_pe_reg_blk_dos_size_t;

typedef struct __pe_reg_blk_pmac_key_t {
   uint32 valid                :                1;
   uint32 mask_of_source_port  :                1;
   uint32 mask_of_destination_port :                1;
   uint32 mask_of_ip_protocol  :                1;
   uint32 mask_of_subtype      :                1;
   uint32 mask_of_opcode       :                1;
   uint32 mask_l4_status       :                1;
   uint32 mask_ip_frag         :                1;
   uint32 mask_of_ip_status    :                1;
   uint32 mask_of_framing_type :                1;
   uint32 mask_of_ethertype    :                1;
   uint32 mask_of_da           :                1;
   uint32 source_port_number   :               16;
   uint32 destination_port_number :               16;
   uint32 ip_protocol          :                8;
   uint32 subtype              :                8;
   uint32 opcode               :                8;
   uint32 l4_status            :                2;
   uint32 ip_frag              :                3;
   uint32 ip_status            :                2;
   uint32 framing_type         :                2;
   uint32 e_type               :               16;
   uint32 da                   :               48;
} ds_pe_reg_blk_pmac_key_t;

typedef struct __pe_reg_blk_port2vlan_t {
   uint32 ivm_index            :               12;
} ds_pe_reg_blk_port2vlan_t;

typedef struct __pe_reg_blk_ivm_x_reg_t {
   uint32 valid                :                1;
   uint32 cvid                 :               12;
   uint32 svid                 :               12;
   uint32 framing_type         :                2;
   uint32 ctag_status          :                2;
   uint32 stag_status          :                2;
   uint32 ether_type           :               16;
   uint32 sa                   :               48;
   uint32 sport                :                6;
} ds_pe_reg_blk_ivm_x_reg_t;

typedef struct __pe_reg_blk_ivm_x_mask_reg_t {
   uint32 cvid_mask            :               12;
   uint32 svid_mask            :               12;
   uint32 framing_type_mask    :                1;
   uint32 ctag_status_mask     :                1;
   uint32 stag_status_mask     :                1;
   uint32 ether_type_mask      :                1;
   uint32 sa_mask              :                6;
   uint32 sport_mask           :                1;
} ds_pe_reg_blk_ivm_x_mask_reg_t;

typedef struct __pe_reg_blk_vlan_port_ctrl_t {
   uint32 key_type1            :                4;
   uint32 key_type2            :                4;
   uint32 range_vid_mode       :                2;
   uint32 vrange_idx           :                2;
   uint32 vrange_en            :                1;
} ds_pe_reg_blk_vlan_port_ctrl_t;

typedef struct __pe_reg_blk_vlan_hash_ctrl_t {
   uint32 hash_seed            :                8;
} ds_pe_reg_blk_vlan_hash_ctrl_t;

typedef struct __pe_reg_blk_vlan_range_t {
   uint32 vlan3_max            :               12;
   uint32 vlan3_min            :               12;
   uint32 reserved0            :                8;
   uint32 vlan2_max            :               12;
   uint32 vlan2_min            :               12;
   uint32 reserved1            :                8;
   uint32 vlan1_max            :               12;
   uint32 vlan1_min            :               12;
   uint32 reserved2            :                8;
   uint32 vlan0_max            :               12;
   uint32 vlan0_min            :               12;
} ds_pe_reg_blk_vlan_range_t;

typedef struct __pe_reg_blk_evm_miss_t {
   uint32 evm_ut_miss          :                1;
   uint32 evm_t_miss_drop      :                1;
   uint32 evm_ut_miss_drop     :                1;
   uint32 evm_index            :               12;
} ds_pe_reg_blk_evm_miss_t;

typedef struct __pe_reg_blk_udf_cam_t {
   uint32 l4_dport             :               16;
   uint32 l4_sport             :               16;
   uint32 l4_type              :                3;
   uint32 fragment_flag        :                2;
   uint32 ip_option            :                1;
   uint32 ip_protocol          :                8;
   uint32 ethtype              :               16;
   uint32 l2_type              :                2;
   uint32 l2_tag_status        :                2;
   uint32 sport_bitmap         :               26;
   uint32 port_type            :                2;
   uint32 valid                :                1;
} ds_pe_reg_blk_udf_cam_t;

typedef struct __pe_reg_blk_udf_port_ctrl_t {
   uint32 bitmap_mode          :               26;
} ds_pe_reg_blk_udf_port_ctrl_t;

typedef struct __pe_reg_blk_udf_offset_t {
   uint32 udf3_offset          :                5;
   uint32 udf2_offset          :                5;
   uint32 udf1_offset          :                5;
   uint32 udf0_offset          :                5;
   uint32 udf3_base_type       :                2;
   uint32 udf2_base_type       :                2;
   uint32 udf1_base_type       :                2;
   uint32 udf0_base_type       :                2;
} ds_pe_reg_blk_udf_offset_t;

typedef struct __pe_reg_blk_acl_global_key_mode_t {
   uint32 key_mode             :                2;
} ds_pe_reg_blk_acl_global_key_mode_t;

typedef struct __pe_reg_blk_acl_global_key_ctrl_t {
   uint32 mac_sel              :                1;
   uint32 ipv6_sa32_sel        :                5;
   uint32 ipv6_da32_sel        :                5;
   uint32 ipv6_addr1_mode      :                1;
   uint32 ipv6_addr2_mode      :                1;
   uint32 vid_mode             :                1;
   uint32 dscp_mode            :                1;
} ds_pe_reg_blk_acl_global_key_ctrl_t;

typedef struct __pe_reg_blk_acl_port_key_config_t {
   uint32 key_range_en         :                9;
   uint32 key3_udf_mode        :                1;
   uint32 slice7_key_mode      :                4;
   uint32 slice6_key_mode      :                4;
   uint32 slice5_key_mode      :                4;
   uint32 slice4_key_mode      :                4;
   uint32 slice3_key_mode      :                4;
   uint32 slice2_key_mode      :                4;
   uint32 slice1_key_mode      :                4;
   uint32 slice0_key_mode      :                4;
   uint32 vid_sel              :                2;
   uint32 bitmap_mode          :                1;
   uint32 acl_en               :                1;
} ds_pe_reg_blk_acl_port_key_config_t;

typedef struct __pe_reg_blk_acl_range_check_t {
   uint32 valid                :                1;
   uint32 optype               :                2;
   uint32 max_val              :               16;
   uint32 min_val              :               16;
} ds_pe_reg_blk_acl_range_check_t;

typedef struct __pe_reg_blk_acl_quad_slice_config_t {
   uint32 quad_mode            :                4;
} ds_pe_reg_blk_acl_quad_slice_config_t;

typedef struct __pe_reg_blk_acl_slice_key_config_t {
   uint32 key_type             :                2;
} ds_pe_reg_blk_acl_slice_key_config_t;

typedef struct __pe_reg_blk_loopback_profile_t {
   uint32 loopback_fwd_mode    :                1;
   uint32 l4port_swap_enable   :                1;
   uint32 sip_unicast_act      :                2;
   uint32 sip_multicast_act    :                1;
   uint32 dip_multicast_act    :                1;
   uint32 dip_unicast_act      :                1;
   uint32 sa_unicast_act       :                2;
   uint32 sa_multicast_act     :                1;
   uint32 da_multicast_act     :                1;
   uint32 da_unicast_act       :                1;
   uint32 opcode_lsb_zero      :                1;
   uint32 icmp_ping_resp       :                1;
   uint32 icmp_2lsb_swap       :                1;
   uint32 twamp_edit           :                1;
   uint32 ttl_insert           :                1;
   uint32 slm_resp             :                1;
   uint32 rmepid               :               13;
} ds_pe_reg_blk_loopback_profile_t;

typedef struct __qos_mem_blk_stc_meter_ctrl_t {
   uint32 drop_thd             :               12;
   uint32 bucket_grain         :                3;
   uint32 refresh_cnt          :               19;
   uint32 meter_delta          :                1;
   uint32 meter_mode           :                1;
   uint32 meter_en             :                1;
} ds_qos_mem_blk_stc_meter_ctrl_t;

typedef struct __qos_mem_blk_stc_meter_cnt_t {
   uint32 b0_cnt               :               29;
} ds_qos_mem_blk_stc_meter_cnt_t;

typedef struct __qos_mem_blk_pri_lplc_map_table_t {
   uint32 local_pri            :                4;
   uint32 local_color          :                2;
} ds_qos_mem_blk_pri_lplc_map_table_t;

typedef struct __qos_mem_blk_lplc_pri_map_table_t {
   uint32 dscp                 :                6;
   uint32 scos                 :                4;
} ds_qos_mem_blk_lplc_pri_map_table_t;

typedef struct __qos_mem_blk_color_map_table_t {
   uint32 map_lp_en            :                1;
   uint32 map_scos_en          :                1;
   uint32 map_dscp_en          :                1;
   uint32 red_lp               :                4;
   uint32 yellow_lp            :                4;
   uint32 green_lp             :                4;
   uint32 red_scos             :                4;
   uint32 yellow_scos          :                4;
   uint32 green_scos           :                4;
   uint32 red_dscp             :                6;
   uint32 yellow_dscp          :                6;
   uint32 green_dscp           :                6;
} ds_qos_mem_blk_color_map_table_t;

typedef struct __qos_mem_blk_ingress_meter_ctrl_t {
   uint32 inservice_mode       :                1;
   uint32 inservice_id         :               10;
   uint32 drop_mode            :                2;
   uint32 color_map_index      :                6;
   uint32 meter_delta          :                1;
   uint32 meter_link           :                2;
   uint32 cm                   :                1;
   uint32 meter_mode           :                2;
   uint32 bucket_grain         :                3;
   uint32 b0_freshcount        :               19;
   uint32 b0_bucketsize        :               12;
   uint32 b1_freshcount        :               19;
   uint32 b1_bucketsize        :               12;
   uint32 meter_en             :                1;
} ds_qos_mem_blk_ingress_meter_ctrl_t;

typedef struct __qos_mem_blk_ingress_meter_cnt_t {
   uint32 b0_cnt               :               29;
   uint32 b1_cnt               :               29;
} ds_qos_mem_blk_ingress_meter_cnt_t;

typedef struct __qos_mem_blk_ingress_counter_ctrl_t {
   uint32 ctrl                 :                3;
} ds_qos_mem_blk_ingress_counter_ctrl_t;

typedef struct __qos_mem_blk_ingress_counter_table_t {
   uint32 byte_cnt             :               46;
   uint32 frame_cnt            :               32;
} ds_qos_mem_blk_ingress_counter_table_t;

typedef struct __qos_mem_blk_ingress_counter_table_view1_t {
   uint32 pre_drop_byte_cnt    :               39;
   uint32 post_drop_byte_cnt   :               39;
} ds_qos_mem_blk_ingress_counter_table_view1_t;

typedef struct __qos_mem_blk_ingress_counter_table_view2_t {
   uint32 red_frame_cnt        :               30;
   uint32 yellow_frame_cnt     :               16;
   uint32 green_frame_cnt      :               32;
} ds_qos_mem_blk_ingress_counter_table_view2_t;

typedef struct __qos_mem_blk_ingress_counter_table_view3_t {
   uint32 stc_drop_cnt         :               18;
   uint32 meter_drop_cnt       :               15;
   uint32 arl_frame_cnt        :               15;
   uint32 vlan_frame_cnt       :               15;
   uint32 acl_frame_cnt        :               15;
} ds_qos_mem_blk_ingress_counter_table_view3_t;

typedef struct __qos_mem_blk_qos_port_drop_cnt_t {
   uint32 in_cnt               :               32;
   uint32 out_cnt              :               32;
   uint32 stc_drop_cnt         :               32;
   uint32 irc_drop_cnt         :               32;
   uint32 macro_drop           :               32;
   uint32 micro_drop           :               32;
} ds_qos_mem_blk_qos_port_drop_cnt_t;

typedef struct __qos_reg_blk_cpu_access_req_t {
   uint32 req                  :                1;
   uint32 req_type             :                1;
   uint32 page                 :                6;
   uint32 addr                 :               24;
} ds_qos_reg_blk_cpu_access_req_t;

typedef struct __qos_reg_blk_cpu_access_wdata_t {
   uint32 data                 :              256;
} ds_qos_reg_blk_cpu_access_wdata_t;

typedef struct __qos_reg_blk_cpu_access_rdata_t {
   uint32 complete             :                1;
   uint32 data                 :              256;
} ds_qos_reg_blk_cpu_access_rdata_t;

typedef struct __qos_reg_blk_glb_meter_ctrl_t {
   uint32 bypass_ptp_irc_meter :                1;
   uint32 bypass_oam_irc_meter :                1;
   uint32 bypass_acl_irc_meter :                1;
   uint32 bypass_ptp_stc_meter :                1;
   uint32 bypass_oam_stc_meter :                1;
   uint32 bypass_acl_stc_meter :                1;
   uint32 meter_gapbyte        :                5;
   uint32 meter_borrow         :                1;
   uint32 irc_stc_loc          :                2;
   uint32 copy_irc_en          :                1;
   uint32 drop_irc_en          :                1;
   uint32 stc_l2mc_mode        :                1;
   uint32 stc_mlf_mode         :                1;
   uint32 copy_stc_en          :                1;
   uint32 drop_stc_en          :                1;
   uint32 dlf_stc_en           :                1;
   uint32 mlf_stc_en           :                1;
   uint32 l2mc_stc_en          :                1;
   uint32 bc_stc_en            :                1;
   uint32 dlf_stc_index        :                2;
   uint32 mlf_stc_index        :                2;
   uint32 l2mc_stc_index       :                2;
   uint32 bc_stc_index         :                2;
   uint32 itu_mode             :                1;
   uint32 ingress_meter_mode   :                1;
   uint32 egress_meter_mode    :                1;
} ds_qos_reg_blk_glb_meter_ctrl_t;

typedef struct __qos_reg_blk_eth_refresh_cfg_t {
   uint32 multi_param          :               12;
   uint32 div_param            :               24;
} ds_qos_reg_blk_eth_refresh_cfg_t;

typedef struct __qos_reg_blk_port_irc_admission_state_t {
   uint32 state                :                2;
} ds_qos_reg_blk_port_irc_admission_state_t;

typedef struct __qos_reg_blk_port_irc_meter_ctrl_t {
   uint32 drop_thd             :               12;
   uint32 pause_thd            :               12;
   uint32 cancel_thd           :               12;
   uint32 pause_en             :                1;
   uint32 bucket_grain         :                3;
   uint32 refresh_cnt          :               19;
   uint32 meter_delta          :                1;
   uint32 meter_mode           :                1;
   uint32 meter_en             :                1;
} ds_qos_reg_blk_port_irc_meter_ctrl_t;

typedef struct __qos_reg_blk_port_stc_mapping_t {
   uint32 dlf_stc_en           :                1;
   uint32 mlf_stc_en           :                1;
   uint32 l2mc_stc_en          :                1;
   uint32 bc_stc_en            :                1;
   uint32 dlf_stc_index        :                2;
   uint32 mlf_stc_index        :                2;
   uint32 l2mc_stc_index       :                2;
   uint32 bc_stc_index         :                2;
} ds_qos_reg_blk_port_stc_mapping_t;

typedef struct __qos_reg_blk_port_stc_base_ctrl_t {
   uint32 port_stc_en          :                1;
   uint32 stc_base_index       :                7;
} ds_qos_reg_blk_port_stc_base_ctrl_t;

typedef struct __qos_reg_blk_lp2qp_map_table_t {
   uint32 egport_qp            :                3;
} ds_qos_reg_blk_lp2qp_map_table_t;

typedef struct __qos_reg_blk_counter_ctrl_t {
   uint32 cnt_rc_en            :                1;
} ds_qos_reg_blk_counter_ctrl_t;

typedef struct __qos_reg_blk_intrusive_ingress_mon_state_t {
   uint32 meter_overflow       :                1;
   uint32 meter_underflow      :                1;
   uint32 sec_rate             :               32;
   uint32 test_not_green_cnt   :               16;
} ds_qos_reg_blk_intrusive_ingress_mon_state_t;

typedef struct __qos_reg_blk_intrusive_egress_mon_state_t {
   uint32 meter_overflow       :                1;
   uint32 meter_underflow      :                1;
   uint32 sec_rate             :               32;
   uint32 test_not_green_cnt   :               16;
} ds_qos_reg_blk_intrusive_egress_mon_state_t;

typedef struct __qos_reg_blk_ingress_intrusive_alm_reg_t {
   uint32 not_green_meter_id   :               11;
   uint32 overflow_meter_id    :               11;
   uint32 underflow_meter_id   :               11;
   uint32 not_green_cnt        :               15;
   uint32 overflow_cnt         :               15;
   uint32 underflow_cnt        :               15;
} ds_qos_reg_blk_ingress_intrusive_alm_reg_t;

typedef struct __qos_reg_blk_egress_intrusive_alm_reg_t {
   uint32 not_green_meter_id   :                8;
   uint32 overflow_meter_id    :                8;
   uint32 underflow_meter_id   :                8;
   uint32 not_green_cnt        :               15;
   uint32 overflow_cnt         :               15;
   uint32 underflow_cnt        :               15;
} ds_qos_reg_blk_egress_intrusive_alm_reg_t;

typedef struct __qos_reg_blk_meter_mon_ctrl_t {
   uint32 meter_monitor_index  :               12;
   uint32 meter_monitor_en     :                1;
} ds_qos_reg_blk_meter_mon_ctrl_t;

typedef struct __qos_reg_blk_meter_mon_state_t {
   uint32 bucket1_cnt          :               29;
   uint32 bucket0_cnt          :               29;
} ds_qos_reg_blk_meter_mon_state_t;

